TY - GEN
T1 - An open electronic system level multi-SPARC virtual platform and its toolchain
AU - Fang, Pin Hao
AU - Wang, Yu Lin
AU - Chen, Zhong Ho
AU - Su, Alvin W.Y.
AU - Shieh, Ce Kuen
PY - 2010
Y1 - 2010
N2 - We present a multi-core virtual platform which follows single-core architecture, SPARC v8, available as an open source development suite. The proposed multi-SPARC system operates at electronic system level to accelerate its simulation speed. TLM channels are devised to connect the processors. To simplify the use of the proposed virtual platform, we define some specific APIs for data transaction and developers can simply follow the pre-defined protocol and complete the data transaction. We also implement the TLM interface for external modules to communicate with the host virtual platform. Furthermore, the proposed virtual platform is capable of running multiple applications with dynamic loading of application programs in run time. That means the multiple applications could execute sequentially without pre-loading all programs when initialized. The virtual platform with 4 SPARC cores can execute up to 1605.88K cycles per second on a 2.4 GHz Core 2 Duo machine. Moreover, the developers do not take too much effort to get used to our virtual platform, since its architecture follows the traditional one, and they could concentrate on architecture implementation as well.
AB - We present a multi-core virtual platform which follows single-core architecture, SPARC v8, available as an open source development suite. The proposed multi-SPARC system operates at electronic system level to accelerate its simulation speed. TLM channels are devised to connect the processors. To simplify the use of the proposed virtual platform, we define some specific APIs for data transaction and developers can simply follow the pre-defined protocol and complete the data transaction. We also implement the TLM interface for external modules to communicate with the host virtual platform. Furthermore, the proposed virtual platform is capable of running multiple applications with dynamic loading of application programs in run time. That means the multiple applications could execute sequentially without pre-loading all programs when initialized. The virtual platform with 4 SPARC cores can execute up to 1605.88K cycles per second on a 2.4 GHz Core 2 Duo machine. Moreover, the developers do not take too much effort to get used to our virtual platform, since its architecture follows the traditional one, and they could concentrate on architecture implementation as well.
UR - https://www.scopus.com/pages/publications/79851507130
UR - https://www.scopus.com/pages/publications/79851507130#tab=citedBy
U2 - 10.1109/COMPSYM.2010.5685464
DO - 10.1109/COMPSYM.2010.5685464
M3 - Conference contribution
AN - SCOPUS:79851507130
SN - 9781424476404
T3 - ICS 2010 - International Computer Symposium
SP - 478
EP - 482
BT - ICS 2010 - International Computer Symposium
T2 - 2010 International Computer Symposium, ICS 2010
Y2 - 16 December 2010 through 18 December 2010
ER -