An SOC test integration platform and its industrial realization

Kuo Liang Cheng, Jing Reng Huang, Chih Wea Wang, Chih Yen Lo, Li Ming Denq, Chih Tsun Huang, Cheng Wen Wu, Shin Wei Hung, Jye Yuan Lee

研究成果: Conference article

7 引文 斯高帕斯(Scopus)

摘要

One of the major costs in system-on-chip (SOC) development is test cost, especially the cost related to test integration. Although there have been plenty of research works on individual topics about SOC testing, few of them took into account the practical integration issues. In this paper, we stress the practical SOC test integration issues, including real problems found in test scheduling, test 10 reduction, timing of functional test, scan 10 sharing, etc. A test scheduling method is proposed based on our test architecture and test access mechanism (TAM), considering 10 resource constraints. Detailed scheduling further reduces the overall test time of the system chip. We also present a test wrapper architecture that supports the coexistence of scan test and functional test. The test integration platform has been applied to an industrial SOC case. The chip has been designed and fabricated. The measurement results justify the approach -simple and efficient, i.e., short test integration cost, short test time, and small area overhead.

原文English
頁(從 - 到)1213-1222
頁數10
期刊Proceedings - International Test Conference
出版狀態Published - 2004 十二月 1
事件Proceedings - International Test Conference 2004 - Charlotte, NC, United States
持續時間: 2004 十月 262004 十月 28

    指紋

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

引用此

Cheng, K. L., Huang, J. R., Wang, C. W., Lo, C. Y., Denq, L. M., Huang, C. T., Wu, C. W., Hung, S. W., & Lee, J. Y. (2004). An SOC test integration platform and its industrial realization. Proceedings - International Test Conference, 1213-1222.