TY - GEN
T1 - An Ultra-Lightweight Time Period CNN Based Model with AI Accelerator Design for Arrhythmia Classification
AU - Lee, Shuenn Yuh
AU - Tseng, Wei Cheng
AU - Chen, Ju Yi
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - This work proposes an arrhythmia classification system. The algorithm includes naive electrocardiography (ECG) data preprocessing procedures that apply to various ECG databases. Additionally, the paper presents an ultra-lightweight model designed for arrhythmia classification, which combines a Convolutional Neural Network (CNN) with long-term heart rate information to enhance the performance of the model. The proposed model was trained and tested using the MIT-BIH and NCKU-CBIC database, following the classification standards of the Association for the Advancement of Medical Instrumentation (AAMI), achieving an accuracy of 98.5% and 97.1%. Furthermore, this work proposes a customized artificial intelligence (AI) accelerator for hardware implementation, which leverages a parallelized processing element (PE) array architecture and hybrid stationary techniques to achieve high-performance computing. The chip implementation achieves a power consumption of 122 μW, a classification latency of 6.8 ms, and an energy efficiency of 0.83 μJ/classification.
AB - This work proposes an arrhythmia classification system. The algorithm includes naive electrocardiography (ECG) data preprocessing procedures that apply to various ECG databases. Additionally, the paper presents an ultra-lightweight model designed for arrhythmia classification, which combines a Convolutional Neural Network (CNN) with long-term heart rate information to enhance the performance of the model. The proposed model was trained and tested using the MIT-BIH and NCKU-CBIC database, following the classification standards of the Association for the Advancement of Medical Instrumentation (AAMI), achieving an accuracy of 98.5% and 97.1%. Furthermore, this work proposes a customized artificial intelligence (AI) accelerator for hardware implementation, which leverages a parallelized processing element (PE) array architecture and hybrid stationary techniques to achieve high-performance computing. The chip implementation achieves a power consumption of 122 μW, a classification latency of 6.8 ms, and an energy efficiency of 0.83 μJ/classification.
UR - http://www.scopus.com/inward/record.url?scp=85198543133&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85198543133&partnerID=8YFLogxK
U2 - 10.1109/ISCAS58744.2024.10557831
DO - 10.1109/ISCAS58744.2024.10557831
M3 - Conference contribution
AN - SCOPUS:85198543133
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - ISCAS 2024 - IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024
Y2 - 19 May 2024 through 22 May 2024
ER -