TY - JOUR
T1 - An Ultralow-Power OOK/BFSK/DBPSK Wake-Up Receiver Based on Injection-Locked Oscillator
AU - Cheng, Kuang Wei
AU - Chen, Shih En
N1 - Funding Information:
Manuscript received January 21, 2021; revised March 26, 2021; accepted April 8, 2021. Date of publication April 28, 2021; date of current version June 29, 2021. This work was supported in part by the Ministry of Science and Technology, Taiwan. (Corresponding author: Kuang-Wei Cheng.) The authors are with the Department of Electrical Engineering, National Cheng Kung University, Tainan 70101, Taiwan (e-mail: [email protected]).
Publisher Copyright:
© 1993-2012 IEEE.
PY - 2021/7
Y1 - 2021/7
N2 - This article presents a high-sensitivity and high energy efficiency wake-up receiver (WuRx) based on an injection-locked oscillator (ILO) and an envelope detector to provide the capabilities of reliable demodulation for ON-OFF keying (OOK), binary frequency shift keying (BFSK), and differential binary phase shift keying (DBPSK) demodulation schemes. A 54-μW 433-MHz multimode WuRx is implemented in a 0.18-μ m CMOS process. For a data rate of 200 kb/s and a bit error rate (BER) <0.1%, the receiver achieves sensitivities of-80/-78/-77 dBm under the OOK/BFSK/DBPSK demodulation schemes, respectively. Furthermore, incorporating an external loop antenna with a reception of an ILO, the receiver features a low-power mode of just 11μW with a sensitivity of at least-71 dBm.
AB - This article presents a high-sensitivity and high energy efficiency wake-up receiver (WuRx) based on an injection-locked oscillator (ILO) and an envelope detector to provide the capabilities of reliable demodulation for ON-OFF keying (OOK), binary frequency shift keying (BFSK), and differential binary phase shift keying (DBPSK) demodulation schemes. A 54-μW 433-MHz multimode WuRx is implemented in a 0.18-μ m CMOS process. For a data rate of 200 kb/s and a bit error rate (BER) <0.1%, the receiver achieves sensitivities of-80/-78/-77 dBm under the OOK/BFSK/DBPSK demodulation schemes, respectively. Furthermore, incorporating an external loop antenna with a reception of an ILO, the receiver features a low-power mode of just 11μW with a sensitivity of at least-71 dBm.
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U2 - 10.1109/TVLSI.2021.3073166
DO - 10.1109/TVLSI.2021.3073166
M3 - Article
AN - SCOPUS:85105082721
SN - 1063-8210
VL - 29
SP - 1379
EP - 1391
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 7
M1 - 9417008
ER -