TY - GEN
T1 - An undershoot/overshoot-suppressed current-mode buck converter with voltage-setting control for type-II compensator
AU - Wang, Pai Yi
AU - Huang, Szu Yu
AU - Fang, Kuan Yu
AU - Kuo, Tai Haur
PY - 2016/1/19
Y1 - 2016/1/19
N2 - Current-mode control is frequently used in dc-dc buck converters. Many current-mode buck converters apply type-II compensators for obtaining high loop gain to reduce the steady-state error and maintaining the loop stability with restricted bandwidth. However, when large load-current transients occur, significant transient undershoot/overshoot is generated due to the restricted loop bandwidth. In response, a type-II compensator with the proposed voltage-setting control (VSC) is presented in this paper. By simply setting the voltage of the compensation capacitor and the input voltage of the compensator, the proposed VSC, which is activated by a transient detector, greatly suppresses the transient undershoot and overshoot. Implemented in 0.35μm CMOS process, this work occupies 0.91mm2 including pads, and features a peak efficiency of 96.3%. With the proposed method, the maximum undershoot and overshoot are respectively suppressed from 150mV to 58mV and 92mV to 62mV for ± 1A load current steps.
AB - Current-mode control is frequently used in dc-dc buck converters. Many current-mode buck converters apply type-II compensators for obtaining high loop gain to reduce the steady-state error and maintaining the loop stability with restricted bandwidth. However, when large load-current transients occur, significant transient undershoot/overshoot is generated due to the restricted loop bandwidth. In response, a type-II compensator with the proposed voltage-setting control (VSC) is presented in this paper. By simply setting the voltage of the compensation capacitor and the input voltage of the compensator, the proposed VSC, which is activated by a transient detector, greatly suppresses the transient undershoot and overshoot. Implemented in 0.35μm CMOS process, this work occupies 0.91mm2 including pads, and features a peak efficiency of 96.3%. With the proposed method, the maximum undershoot and overshoot are respectively suppressed from 150mV to 58mV and 92mV to 62mV for ± 1A load current steps.
UR - http://www.scopus.com/inward/record.url?scp=84963791916&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84963791916&partnerID=8YFLogxK
U2 - 10.1109/ASSCC.2015.7387487
DO - 10.1109/ASSCC.2015.7387487
M3 - Conference contribution
AN - SCOPUS:84963791916
T3 - 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings
BT - 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015
Y2 - 9 November 2015 through 11 November 2015
ER -