Analysis and control of hysteresis in PD/SOI CMOS

M. M. Pelella; J. G. Fossum; M. H. Chiang; G. O. Workman; C. R. Tretz

Analysis and control of hysteresis in PD/SOI CMOS

M. M. Pelella
, J. G. Fossum
, M. H. Chiang
, G. O. Workman
, C. R. Tretz

奈米積體電路工程博士學位學程

研究成果: Conference article › 同行評審

13 引文斯高帕斯（Scopus）

摘要

A new methodology to characterize and analyze hysteresis in PD/SOI CMOS inverter-based circuits, including its true worst case, is defined, and new insight into the underlying physics is provided. The methodology is used to explore novel device/circuit designs for controlling hysteresis as the PD/SOI CMOS technology is scaled to <100nm.

原文	English
頁（從 - 到）	831-834
頁數	4
期刊	Technical Digest - International Electron Devices Meeting
出版狀態	Published - 1999
事件	1999 IEEE International Devices Meeting (IEDM) - Washington, DC, USA 持續時間: 1999 12月 5 → 1999 12月 8

All Science Journal Classification (ASJC) codes

電子、光磁材料
凝聚態物理學
電氣與電子工程
材料化學

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引用此

@article{e17e8710e20e4fcdbded35041d52fd0d,

title = "Analysis and control of hysteresis in PD/SOI CMOS",

abstract = "A new methodology to characterize and analyze hysteresis in PD/SOI CMOS inverter-based circuits, including its true worst case, is defined, and new insight into the underlying physics is provided. The methodology is used to explore novel device/circuit designs for controlling hysteresis as the PD/SOI CMOS technology is scaled to <100nm.",

author = "Pelella, \{M. M.\} and Fossum, \{J. G.\} and Chiang, \{M. H.\} and Workman, \{G. O.\} and Tretz, \{C. R.\}",

year = "1999",

language = "English",

pages = "831--834",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "1999 IEEE International Devices Meeting (IEDM) ; Conference date: 05-12-1999 Through 08-12-1999",

}

TY - JOUR

T1 - Analysis and control of hysteresis in PD/SOI CMOS

AU - Pelella, M. M.

AU - Fossum, J. G.

AU - Chiang, M. H.

AU - Workman, G. O.

AU - Tretz, C. R.

PY - 1999

Y1 - 1999

N2 - A new methodology to characterize and analyze hysteresis in PD/SOI CMOS inverter-based circuits, including its true worst case, is defined, and new insight into the underlying physics is provided. The methodology is used to explore novel device/circuit designs for controlling hysteresis as the PD/SOI CMOS technology is scaled to <100nm.

AB - A new methodology to characterize and analyze hysteresis in PD/SOI CMOS inverter-based circuits, including its true worst case, is defined, and new insight into the underlying physics is provided. The methodology is used to explore novel device/circuit designs for controlling hysteresis as the PD/SOI CMOS technology is scaled to <100nm.

UR - https://www.scopus.com/pages/publications/0033347311

UR - https://www.scopus.com/pages/publications/0033347311#tab=citedBy

M3 - Conference article

AN - SCOPUS:0033347311

SN - 0163-1918

SP - 831

EP - 834

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - 1999 IEEE International Devices Meeting (IEDM)

Y2 - 5 December 1999 through 8 December 1999

ER -

Analysis and control of hysteresis in PD/SOI CMOS

摘要

All Science Journal Classification (ASJC) codes

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