The high-order Σ-Δ modulator is an appropriate approach for high-bandwidth, high-resolution A/D conversion. However, non-ideal effects such as the finite op-amp gain and the capacitor mismatch have great impacts on its performance at a low oversampling ratio. To achieve greater performance under the inevitable non-ideal effects, we explore several multiple-bit schemes, based on our CIQE high-order Σ-Δ architecture, to remove the non-ideal deterioration. Design rules of these multiple-bit schemes are developed and verified by extensive simulations.
|出版狀態||Published - 1997 一月 1|
|事件||Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC - Chiba, Jpn|
持續時間: 1997 一月 28 → 1997 一月 31
|Conference||Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC|
|期間||97-01-28 → 97-01-31|
All Science Journal Classification (ASJC) codes