Analysis and design of multiple-bit high-order Σ-Δ modulator

Hao Chiao Hong, Bin Hong Lin, Cheng Wen Wu

研究成果: Paper同行評審

3 引文 斯高帕斯(Scopus)

摘要

The high-order Σ-Δ modulator is an appropriate approach for high-bandwidth, high-resolution A/D conversion. However, non-ideal effects such as the finite op-amp gain and the capacitor mismatch have great impacts on its performance at a low oversampling ratio. To achieve greater performance under the inevitable non-ideal effects, we explore several multiple-bit schemes, based on our CIQE high-order Σ-Δ architecture, to remove the non-ideal deterioration. Design rules of these multiple-bit schemes are developed and verified by extensive simulations.

原文English
頁面419-424
頁數6
出版狀態Published - 1997 一月 1
事件Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC - Chiba, Jpn
持續時間: 1997 一月 281997 一月 31

Conference

ConferenceProceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC
城市Chiba, Jpn
期間97-01-2897-01-31

All Science Journal Classification (ASJC) codes

  • 電腦科學應用
  • 電腦繪圖與電腦輔助設計
  • 電氣與電子工程

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