TY - JOUR
T1 - Analysis and implementation of a CMOS even harmonic mixer with current reuse for heterodyne/direct conversion receivers
AU - Lee, Shuenn Yuh
AU - Huang, Ming Feng
AU - Kuo, Chung J.
N1 - Funding Information:
Manuscript received June 14, 2004; revised December 9, 2004. This work was supported by the Chip Implementation Center (CIC), the National Nano Device Laboratories (NDL), the Wireless Communication Laboratories (WCLab), and the National Science Council (NSC), Taiwan, R.O.C., by Grant NSC 92-2220-E-194-013. This paper was recommended by Associate Editor I. M. Filanovsky.
PY - 2005/9
Y1 - 2005/9
N2 - This paper presents a novel topology for the even harmonic mixer (EHM). The proposed mixer employs a current reuse circuit in the RF input stage to improve its linearity, and uses the double frequency technique in the LO input stage to overcome the leakage and dc offset problems for heterodyne and direct conversion receivers, respectively. In addition, the proposed topology also has the advantages of low power consumption and high conversion gain. In order to demonstrate the benefits of the proposed mixer, theoretical analyses of linearity, conversion gain, and noise performance have been described in detail. The measured results reveal that the proposed mixer has a single-end conversion gain of 9.17 dB, third-order input intercept point (IIP3) of - 5.01 dBm, and IIP3/dc of - 6.31 dB, under the supply voltage of 1.8 V, power consumption of 1.35 mW, and LO power of 5 dBm at 900 MHz.
AB - This paper presents a novel topology for the even harmonic mixer (EHM). The proposed mixer employs a current reuse circuit in the RF input stage to improve its linearity, and uses the double frequency technique in the LO input stage to overcome the leakage and dc offset problems for heterodyne and direct conversion receivers, respectively. In addition, the proposed topology also has the advantages of low power consumption and high conversion gain. In order to demonstrate the benefits of the proposed mixer, theoretical analyses of linearity, conversion gain, and noise performance have been described in detail. The measured results reveal that the proposed mixer has a single-end conversion gain of 9.17 dB, third-order input intercept point (IIP3) of - 5.01 dBm, and IIP3/dc of - 6.31 dB, under the supply voltage of 1.8 V, power consumption of 1.35 mW, and LO power of 5 dBm at 900 MHz.
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U2 - 10.1109/TCSI.2005.852487
DO - 10.1109/TCSI.2005.852487
M3 - Article
AN - SCOPUS:27144538971
SN - 1057-7122
VL - 52
SP - 1741
EP - 1751
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 9
ER -