Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits

Cheng Wu Lin, Chung Lin Lee, Jai Ming Lin, Soon Jyh Chang

研究成果: Conference article同行評審

8 引文 斯高帕斯(Scopus)

摘要

Switched capacitors are commonly used in analog design. The circuit performance based on this technique relies on the accuracy of capacitance ratios, which are affected by random and systematic mismatches. To meet the accuracy requirement, designers can increase the layout area of unit capacitors to reduce random mismatch. Since increasing layout area enlarges the distance between unit capacitors, it induces more gradient errors, which results in larger systematic mismatch. Therefore, the better way for reducing the gradient errors is to carefully determine the locations of unit capacitors in a capacitor array. Moreover, the resulting placement must have high capacitance correlation in order to enhance yield. In this paper, we first explore the attributes of a good capacitor placement, which can reduce gradient errors and increase capacitance correlation. Then, an analytical-based approach is proposed to complete capacitor placement considering these issues. Finally, the results are optimized by arbitrarily swapping two unit capacitors. Compared with the simulated annealing based approach, the proposed method not only achieves better placement results but also gets 34x faster for the largest benchmark capacitor array.

原文English
文章編號6386738
頁(從 - 到)635-642
頁數8
期刊IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
DOIs
出版狀態Published - 2012
事件2012 30th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012 - San Jose, CA, United States
持續時間: 2012 十一月 52012 十一月 8

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

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