TY - GEN
T1 - Analyzing the BTI effect on multi-bit retention registers
AU - Lin, Ing Chao
AU - Wang, Yao Te
AU - Yang, Shuen Shiang
AU - Wu, Yi Luen
N1 - Publisher Copyright:
© 2015 The authors and IOS Press. All rights reserved.
Copyright:
Copyright 2015 Elsevier B.V., All rights reserved.
PY - 2015
Y1 - 2015
N2 - As the Bias Temperature Instability (BTI) effect increase the threshold voltage of transistors and decrease transistors speed, it become a major problem for circuit reliability. Retention registers are used in the power gating architecture. These registers can keep the current states in the always-on blocks. However, they suffer from the BTI effect since the always-on block never is turned off. This paper proposes 2-bit and 3-bit parallel multi-bit retention registers and investigates the BTI effect on multi-bit retention registers. This paper also uses the selective transistor sizing technique to reduce the degradation. The proposed the multi-bit retention register architecture and design characteristics can reduce the significant area overhead. The experimental results show that compared with the original Dual Control Balloon Register (DCBR), the 2-bit and 3-bit retention registers can reduce area overhead by 27.1% and 34.7%, respectively.
AB - As the Bias Temperature Instability (BTI) effect increase the threshold voltage of transistors and decrease transistors speed, it become a major problem for circuit reliability. Retention registers are used in the power gating architecture. These registers can keep the current states in the always-on blocks. However, they suffer from the BTI effect since the always-on block never is turned off. This paper proposes 2-bit and 3-bit parallel multi-bit retention registers and investigates the BTI effect on multi-bit retention registers. This paper also uses the selective transistor sizing technique to reduce the degradation. The proposed the multi-bit retention register architecture and design characteristics can reduce the significant area overhead. The experimental results show that compared with the original Dual Control Balloon Register (DCBR), the 2-bit and 3-bit retention registers can reduce area overhead by 27.1% and 34.7%, respectively.
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U2 - 10.3233/978-1-61499-484-8-269
DO - 10.3233/978-1-61499-484-8-269
M3 - Conference contribution
AN - SCOPUS:84926429787
T3 - Frontiers in Artificial Intelligence and Applications
SP - 269
EP - 278
BT - Intelligent Systems and Applications - Proceedings of the International Computer Symposium, ICS 2014
A2 - Chu, William Cheng-Chung
A2 - Yang, Stephen Jenn-Hwa
A2 - Chao, Han-Chieh
PB - IOS Press
T2 - International Computer Symposium, ICS 2014
Y2 - 12 December 2014 through 14 December 2014
ER -