Analyzing the BTI effect on multi-bit retention registers

Ing Chao Lin, Yao Te Wang, Shuen Shiang Yang, Yi Luen Wu

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

摘要

As the Bias Temperature Instability (BTI) effect increase the threshold voltage of transistors and decrease transistors speed, it become a major problem for circuit reliability. Retention registers are used in the power gating architecture. These registers can keep the current states in the always-on blocks. However, they suffer from the BTI effect since the always-on block never is turned off. This paper proposes 2-bit and 3-bit parallel multi-bit retention registers and investigates the BTI effect on multi-bit retention registers. This paper also uses the selective transistor sizing technique to reduce the degradation. The proposed the multi-bit retention register architecture and design characteristics can reduce the significant area overhead. The experimental results show that compared with the original Dual Control Balloon Register (DCBR), the 2-bit and 3-bit retention registers can reduce area overhead by 27.1% and 34.7%, respectively.

原文English
主出版物標題Intelligent Systems and Applications - Proceedings of the International Computer Symposium, ICS 2014
編輯William Cheng-Chung Chu, Stephen Jenn-Hwa Yang, Han-Chieh Chao
發行者IOS Press
頁面269-278
頁數10
ISBN(電子)9781614994831
DOIs
出版狀態Published - 2015
事件International Computer Symposium, ICS 2014 - Taichung, Taiwan
持續時間: 2014 十二月 122014 十二月 14

出版系列

名字Frontiers in Artificial Intelligence and Applications
274
ISSN(列印)0922-6389

Other

OtherInternational Computer Symposium, ICS 2014
國家Taiwan
城市Taichung
期間14-12-1214-12-14

All Science Journal Classification (ASJC) codes

  • Artificial Intelligence

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