TY - JOUR
T1 - Antiwear Leveling Design for SSDs with Hybrid ECC Capability
AU - Ho, Chien Chung
AU - Liu, Yu Ping
AU - Chang, Yuan Hao
AU - Kuo, Tei Wei
N1 - Funding Information:
This work was supported in part by the Ministry of Science and Technology under Grant 104-2221-E-001-020-MY3, Grant 105-3111-Y-001-041, Grant 105-2221-E-001-004-MY2, and Grant 105-2221-E-001-013-MY3.
Publisher Copyright:
© 2016 IEEE.
PY - 2017/2
Y1 - 2017/2
N2 - With the joint considerations of reliability and performance, hybrid error correction code (ECC) becomes an option in the designs of solid-state drives (SSDs). Unfortunately, wear leveling (WL) might result in the early performance degradation to SSDs, which is common with a limited number of P/E cycles, due to the efforts to delay the bit-error-rate growth. In this paper, an anti-WL design is proposed to avoid such a performance problem so that the performance of SSDs with hybrid ECC capability can be improved without sacrificing their reliability. The capability of the proposed design was evaluated by a series of experiments, for which it was shown that the proposed design could greatly improve the read and write performance of SSDs up to 50% without affecting the endurance of the investigated SSDs, compared with traditional approaches.
AB - With the joint considerations of reliability and performance, hybrid error correction code (ECC) becomes an option in the designs of solid-state drives (SSDs). Unfortunately, wear leveling (WL) might result in the early performance degradation to SSDs, which is common with a limited number of P/E cycles, due to the efforts to delay the bit-error-rate growth. In this paper, an anti-WL design is proposed to avoid such a performance problem so that the performance of SSDs with hybrid ECC capability can be improved without sacrificing their reliability. The capability of the proposed design was evaluated by a series of experiments, for which it was shown that the proposed design could greatly improve the read and write performance of SSDs up to 50% without affecting the endurance of the investigated SSDs, compared with traditional approaches.
UR - http://www.scopus.com/inward/record.url?scp=84981727621&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84981727621&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2016.2589318
DO - 10.1109/TVLSI.2016.2589318
M3 - Article
AN - SCOPUS:84981727621
SN - 1063-8210
VL - 25
SP - 488
EP - 501
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 2
M1 - 7527690
ER -