TY - JOUR
T1 - Application of low-frequency clock signals to gate driver circuits
AU - Lin, Chin Lung
AU - Cheng, Mao Hsun
N1 - Funding Information:
The authors would like to thank the Ministry of Science and Technology, Taiwan, for financially supporting this research under contract no. MOST 104-2221-E-006-189-MY3. Also, the authors acknowledge AU Optronics Corporation, Hsinchu, Taiwan, for its technical support.
Publisher Copyright:
© (2017) by SID-the Society for Information Display. All rights reserved.
PY - 2017
Y1 - 2017
N2 - This paper collates design concepts of lowpower gate driver circuits, and our related work is reviewed. Many approaches to power consumption amelioration have been developed and-focus on different parts of circuit structures. Recently, low-frequency clock signals are adopted to further reduce both power consumption and thin-film transistor (TFT) threshold voltage shifts (ΔVTH).
AB - This paper collates design concepts of lowpower gate driver circuits, and our related work is reviewed. Many approaches to power consumption amelioration have been developed and-focus on different parts of circuit structures. Recently, low-frequency clock signals are adopted to further reduce both power consumption and thin-film transistor (TFT) threshold voltage shifts (ΔVTH).
UR - https://www.scopus.com/pages/publications/85044474568
UR - https://www.scopus.com/pages/publications/85044474568#tab=citedBy
U2 - 10.1002/sdtp.11559
DO - 10.1002/sdtp.11559
M3 - Conference article
AN - SCOPUS:85044474568
SN - 0097-966X
VL - 48
SP - 64
EP - 67
JO - Digest of Technical Papers - SID International Symposium
JF - Digest of Technical Papers - SID International Symposium
IS - 1
T2 - SID Symposium, Seminar, and Exhibition 2017, Display Week 2017
Y2 - 21 May 2017 through 26 May 2017
ER -