Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers

Hsiang Chih Hsiao, Chun Wei Chen, Jonas Wang, Ming Der Shieh, Pei Yin Chen

研究成果: Conference contribution

摘要

Cascaded classifier based object detectors are popular for many applications because of their high efficiency. Many researches have been devoted to developing the corresponding hardware accelerators. To reduce the circuit complexity while maintaining sufficient throughput, on-chip memories are commonly partitioned into several banks for parallel data access. However, since the coefficients of feature extraction are irregular, memory access conflict would frequently occur without proper scheduling. The proposed scheme explicitly schedules the access sequence as a post-processing for managing the coefficient memory. By formulating the desired sequence as a graph model, the classical graph coloring theory can then be adopted to solve the scheduling problem. In addition, the proposed graph model also considers the resource constraint on intermediate storage. Experimental results show that the throughput and area-efficiency of the target cascaded classifier can be greatly improved by adopting the proposed scheme as compared to the related work.

原文English
主出版物標題Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781728100739
DOIs
出版狀態Published - 2019 四月
事件22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019 - Cluj-Napoca, Romania
持續時間: 2019 四月 242019 四月 26

出版系列

名字Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019

Conference

Conference22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019
國家Romania
城市Cluj-Napoca
期間19-04-2419-04-26

All Science Journal Classification (ASJC) codes

  • Artificial Intelligence
  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Control and Optimization

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