@inproceedings{635b001c8dd84a4db235a030ab49232d,
title = "ASLCScan: A scan design technique for asynchronous sequential logic circuits",
abstract = "Asynchronous sequential logic circuits (ASLCs) are synthesized with either the Huffman model, referred to as HMASLCs, or with the signal transition graph (STG), referred to as STGASLCs. Based on a single stuck-at fault model, this paper describes fault effects for both HMASLCs and STGASLCs and addresses the similarities and differences between them. The fault effects include redundant faults and state oscillations. Input/output redundancy is a special feature of STGASLCs which relaxes the fundamental mode in HMASLCs. Results of this study show that the faults due to the input/output concurrency cannot be tested without a scan structure. This paper presents a scan design technique, ASLCScan. With this scan structure, the test generation problem is reduced to one of just testing the combinational logic.",
author = "Wey, {Chin Long} and Shieh, {Ming Der} and Fisher, {P. David}",
year = "1993",
month = dec,
day = "1",
language = "English",
isbn = "0818642300",
series = "Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors",
publisher = "Publ by IEEE",
pages = "159--162",
editor = "Anon",
booktitle = "Proceedings - IEEE International Conference on Computer Design",
note = "Proceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers & Processors ; Conference date: 03-10-1993 Through 06-10-1993",
}