ASLCScan: A scan design technique for asynchronous sequential logic circuits

Chin Long Wey, Ming Der Shieh, P. David Fisher

研究成果: Conference contribution

9 引文 斯高帕斯(Scopus)

摘要

Asynchronous sequential logic circuits (ASLCs) are synthesized with either the Huffman model, referred to as HMASLCs, or with the signal transition graph (STG), referred to as STGASLCs. Based on a single stuck-at fault model, this paper describes fault effects for both HMASLCs and STGASLCs and addresses the similarities and differences between them. The fault effects include redundant faults and state oscillations. Input/output redundancy is a special feature of STGASLCs which relaxes the fundamental mode in HMASLCs. Results of this study show that the faults due to the input/output concurrency cannot be tested without a scan structure. This paper presents a scan design technique, ASLCScan. With this scan structure, the test generation problem is reduced to one of just testing the combinational logic.

原文English
主出版物標題Proceedings - IEEE International Conference on Computer Design
主出版物子標題VLSI in Computers and Processors
編輯 Anon
發行者Publ by IEEE
頁面159-162
頁數4
ISBN(列印)0818642300
出版狀態Published - 1993 12月 1
事件Proceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Cambridge, MA, USA
持續時間: 1993 10月 31993 10月 6

出版系列

名字Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Other

OtherProceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers & Processors
城市Cambridge, MA, USA
期間93-10-0393-10-06

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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