Asymmetrical triple-gate FET

Meng Hsueh Chiang, Jeng Nan Lin, Keunwoo Kim, Ching Te Chuang

研究成果: Paper

摘要

A novel triple-gate MOSFET structure with polysilicon gate process is proposed using asymmetrical (n+/p+) polysilicon gates. CMOS-compatible VT's for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed by three-dimensional numerical simulations. Comparisons of device properties with the mid-gap metal gate are presented.

原文English
頁面389-392
頁數4
出版狀態Published - 2007 一月 1
事件12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007 - Vienna, Austria
持續時間: 2007 九月 252007 九月 27

Other

Other12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007
國家Austria
城市Vienna
期間07-09-2507-09-27

指紋

Field effect transistors
Polysilicon
MOSFET
High Performance
Metals
Numerical Simulation
Three-dimensional
Networks (circuits)
Computer simulation

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Modelling and Simulation

引用此文

Chiang, M. H., Lin, J. N., Kim, K., & Chuang, C. T. (2007). Asymmetrical triple-gate FET. 389-392. 論文發表於 12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007, Vienna, Austria.
Chiang, Meng Hsueh ; Lin, Jeng Nan ; Kim, Keunwoo ; Chuang, Ching Te. / Asymmetrical triple-gate FET. 論文發表於 12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007, Vienna, Austria.4 p.
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Chiang, MH, Lin, JN, Kim, K & Chuang, CT 2007, 'Asymmetrical triple-gate FET', 論文發表於 12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007, Vienna, Austria, 07-09-25 - 07-09-27 頁 389-392.

Asymmetrical triple-gate FET. / Chiang, Meng Hsueh; Lin, Jeng Nan; Kim, Keunwoo; Chuang, Ching Te.

2007. 389-392 論文發表於 12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007, Vienna, Austria.

研究成果: Paper

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N2 - A novel triple-gate MOSFET structure with polysilicon gate process is proposed using asymmetrical (n+/p+) polysilicon gates. CMOS-compatible VT's for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed by three-dimensional numerical simulations. Comparisons of device properties with the mid-gap metal gate are presented.

AB - A novel triple-gate MOSFET structure with polysilicon gate process is proposed using asymmetrical (n+/p+) polysilicon gates. CMOS-compatible VT's for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed by three-dimensional numerical simulations. Comparisons of device properties with the mid-gap metal gate are presented.

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Chiang MH, Lin JN, Kim K, Chuang CT. Asymmetrical triple-gate FET. 2007. 論文發表於 12th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007, Vienna, Austria.