Asynchronous design methodology for an efficient implementation of low power ALU

P. Manikandan, B. D. Liu, L. Y. Chiou, G. Sundar, C. R. Mandal

研究成果: Conference contribution

摘要

We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and potentially for low power consumption. The design has been described and implemented to achieve high performance in comparison with the synchronous and available asynchronous design. The experimental result shows significant reduction in the number of transistors as well as delay.

原文English
主出版物標題APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
頁面590-593
頁數4
DOIs
出版狀態Published - 2006 十二月 1
事件APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore
持續時間: 2006 十二月 42006 十二月 6

出版系列

名字IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

OtherAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
國家/地區Singapore
期間06-12-0406-12-06

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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