TY - GEN
T1 - Automated synthesis of asynchronous pipelines
AU - Kuo, Yau Hwang
AU - Lo, Shaw Pyng
N1 - Publisher Copyright:
© 1992 IEEE.
PY - 1992
Y1 - 1992
N2 - This paper proposes a system for the automatic synthesis of asynchronous pipelines. A high-level hardware description language (HDL), called Masil-II, is developed to describe the circuit behavior at algorithmic level. Modified Petri-Net is used as intermediate description. From the intermediate description, several techniques such as clique partitioning, simulated evolution and heuristics are applied to realize the data path synthesis task. Experimental results have confirmed their efficiency.
AB - This paper proposes a system for the automatic synthesis of asynchronous pipelines. A high-level hardware description language (HDL), called Masil-II, is developed to describe the circuit behavior at algorithmic level. Modified Petri-Net is used as intermediate description. From the intermediate description, several techniques such as clique partitioning, simulated evolution and heuristics are applied to realize the data path synthesis task. Experimental results have confirmed their efficiency.
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U2 - 10.1109/ISCAS.1992.230159
DO - 10.1109/ISCAS.1992.230159
M3 - Conference contribution
AN - SCOPUS:0013456013
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 685
EP - 688
BT - 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
Y2 - 10 May 1992 through 13 May 1992
ER -