Automatic synthesis of testable VLSI cellular array multipliers

Cheng Wen Wu, Shun Fan Shu, Kun Jin Lin

研究成果: Article同行評審


We present an application-specific computer-aided design (ASCAD) tool that aids the design of easily testable bit-level cellular array multipliers, including bit-serial, bit-parallel, and block multipliers. The tool, based on a nonlinear space-time transformation algorithm and bit-level cellular array architectures, is a very high-level one. A multiplier designer only needs to specify (1) the multiplicand and the multiplier word lengths, (2) the throughput range, and (3) the multiplier type. The tool then generates a VLSI circuit layout for the multiplier which meets the designer’s specifications, and the circuit is guaranteed to be functionally correct. Our ASCAD tool thus eliminates the design and verification costs associated with manual design. Because it is application-specific, the tool itself is very easy to implement.

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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