Back-gate forward bias method for low-voltage CMOS digital circuits

Ming Jer Chen, Jib Shin Ho, Tzuen Hsi Huang, Chuang Hen Yang, Yeh Ning Jou, Wu Terry

研究成果: Article

34 引文 斯高帕斯(Scopus)

摘要

The back-gate forward bias method suitable for present standard bulk CMOS processes has been promoted for low-voltage digital circuit application. A CMOS inverter employing the method has experimentally exhibited the ability of electrically adjusting the transition region of the dc voltage transfer characteristics. Transient measurement has further shown that the inverter with a back-gate forward bias of 0.4 V can operate at low supply voltages down to 0.6 V without significant loss in switching speed. Guidelines for ensuring proper implementation of the method in a bulk CMOS process has been set up against latch-up, parasitic bipolar, impact ionization, and stand-by current. Following these guidelines, a cost-effective low-power, low-voltage, high-density mixed-mode CMOS analog/digital integrated circuits chip with both reasonable speed and improved precision has been projected for the first time.

原文English
頁(從 - 到)904-910
頁數7
期刊IEEE Transactions on Electron Devices
43
發行號6
DOIs
出版狀態Published - 1996 十二月 1

    指紋

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

引用此