Bayesian neural network chip design for speech recognition system

Jhing Fa Wang, An Nan Suen, Jia Ru Lee, Chung Hsien Wu

研究成果: Paper同行評審

2 引文 斯高帕斯(Scopus)

摘要

The Bayesian Neural Network (BNN) has been widely used as speech recognition template which combines the merits of the Dynamic Programming (DP) and Hidden Markov Model (HMM) methods. However, it is computationally intensive and very costly to implement using DSP component. A single chip implementation of the BNN will drastically reduce the cost and the size of many speech recognition systems. It will also make low cost implementation of real-time speech recognition system possible. In this paper, the implementation of single BNN chip for the real-time speech recognizer is presented. Fabricated in 0.8 μm double-metal CMOS technology, the chip contains approximately 13000 transistors which occupy a 3.1×3.2 mm2 area and has been tested to be fully functional at IMS XL-60 tester.

原文English
頁面2027-2030
頁數4
出版狀態Published - 1995 十二月 1
事件Proceedings of the 1995 IEEE International Conference on Neural Networks. Part 1 (of 6) - Perth, Aust
持續時間: 1995 十一月 271995 十二月 1

Other

OtherProceedings of the 1995 IEEE International Conference on Neural Networks. Part 1 (of 6)
城市Perth, Aust
期間95-11-2795-12-01

All Science Journal Classification (ASJC) codes

  • Software

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