摘要
The Bayesian Neural Network (BNN) has been widely used as speech recognition template which combines the merits of the Dynamic Programming (DP) and Hidden Markov Model (HMM) methods. However, it is computationally intensive and very costly to implement using DSP component. A single chip implementation of the BNN will drastically reduce the cost and the size of many speech recognition systems. It will also make low cost implementation of real-time speech recognition system possible. In this paper, the implementation of single BNN chip for the real-time speech recognizer is presented. Fabricated in 0.8 μm double-metal CMOS technology, the chip contains approximately 13000 transistors which occupy a 3.1×3.2 mm2 area and has been tested to be fully functional at IMS XL-60 tester.
| 原文 | English |
|---|---|
| 頁面 | 2027-2030 |
| 頁數 | 4 |
| 出版狀態 | Published - 1995 十二月 1 |
| 事件 | Proceedings of the 1995 IEEE International Conference on Neural Networks. Part 1 (of 6) - Perth, Aust 持續時間: 1995 十一月 27 → 1995 十二月 1 |
Other
| Other | Proceedings of the 1995 IEEE International Conference on Neural Networks. Part 1 (of 6) |
|---|---|
| 城市 | Perth, Aust |
| 期間 | 95-11-27 → 95-12-01 |
指紋
All Science Journal Classification (ASJC) codes
- Software
引用此文
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Bayesian neural network chip design for speech recognition system. / Wang, Jhing Fa; Suen, An Nan; Lee, Jia Ru; Wu, Chung Hsien.
1995. 2027-2030 論文發表於 Proceedings of the 1995 IEEE International Conference on Neural Networks. Part 1 (of 6), Perth, Aust, .研究成果: Paper
TY - CONF
T1 - Bayesian neural network chip design for speech recognition system
AU - Wang, Jhing Fa
AU - Suen, An Nan
AU - Lee, Jia Ru
AU - Wu, Chung Hsien
PY - 1995/12/1
Y1 - 1995/12/1
N2 - The Bayesian Neural Network (BNN) has been widely used as speech recognition template which combines the merits of the Dynamic Programming (DP) and Hidden Markov Model (HMM) methods. However, it is computationally intensive and very costly to implement using DSP component. A single chip implementation of the BNN will drastically reduce the cost and the size of many speech recognition systems. It will also make low cost implementation of real-time speech recognition system possible. In this paper, the implementation of single BNN chip for the real-time speech recognizer is presented. Fabricated in 0.8 μm double-metal CMOS technology, the chip contains approximately 13000 transistors which occupy a 3.1×3.2 mm2 area and has been tested to be fully functional at IMS XL-60 tester.
AB - The Bayesian Neural Network (BNN) has been widely used as speech recognition template which combines the merits of the Dynamic Programming (DP) and Hidden Markov Model (HMM) methods. However, it is computationally intensive and very costly to implement using DSP component. A single chip implementation of the BNN will drastically reduce the cost and the size of many speech recognition systems. It will also make low cost implementation of real-time speech recognition system possible. In this paper, the implementation of single BNN chip for the real-time speech recognizer is presented. Fabricated in 0.8 μm double-metal CMOS technology, the chip contains approximately 13000 transistors which occupy a 3.1×3.2 mm2 area and has been tested to be fully functional at IMS XL-60 tester.
UR - http://www.scopus.com/inward/record.url?scp=0029514615&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0029514615&partnerID=8YFLogxK
M3 - Paper
AN - SCOPUS:0029514615
SP - 2027
EP - 2030
ER -