Behavior model for comparator-based switched-capacitor SDM with relaxed DEM timing

I. Jen Chao, Chung Lun Hsu, Bin Da Liu, Chun Yueh Huang, Soon Jyh Chang

研究成果: Conference contribution

摘要

This paper proposes a behavior model for comparator-based switched-capacitor (CBSC) circuits by using SIMULINK platform. In this model, the maximum available time is compared with the charge transfer time required in the CBSC circuit to identify whether the currents chosen are suitable or not. The model is efficient to determine the values of the coarse charging current and the fine charging current required for CBSC circuits in a sigma-delta modulator (SDM). To verify the behavior model, a 3rd order SDM which still retains a half of the clock cycle for quantization and dynamic element matching (DEM) is proposed and simulated. The simulation result shows that the value of SNDR achieves 82.23 dB when the sampling rate is 100 MS/s (OSR=16).

原文English
主出版物標題1st International Conference on Green Circuits and Systems, ICGCS 2010
頁面495-498
頁數4
DOIs
出版狀態Published - 2010 九月 20
事件1st International Conference on Green Circuits and Systems, ICGCS 2010 - Shanghai, China
持續時間: 2010 六月 212010 六月 23

出版系列

名字1st International Conference on Green Circuits and Systems, ICGCS 2010

Other

Other1st International Conference on Green Circuits and Systems, ICGCS 2010
國家/地區China
城市Shanghai
期間10-06-2110-06-23

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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