BIFEST: A built-in intermediate fault effect sensing and test generation system for cmos bridging faults

Kuen Jong Lee, Jing Jou Tang, Tsung Chu Huang

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)

摘要

This paper presents BIFEST, an ATPG system that employs the built-in intermediate voltage test technique in an efficient ATPG process to deal with CMOS bridging faults. Fast and accurate calculations of the intermediate bridging voltages and the variant threshold tolerance margins on a resistive bridging fault model are presented. A PODEM-like, PPSFP-based ATPG process is developed to generate test patterns for faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits, called built-in intermediate voltage sensors (BIVSs). By this methodology, almost the same fault coverage as that employing IDOQ testing can be achieved with only logic monitoring required.

原文English
頁(從 - 到)194-218
頁數25
期刊ACM Transactions on Design Automation of Electronic Systems
4
發行號2
DOIs
出版狀態Published - 1999

All Science Journal Classification (ASJC) codes

  • 電腦科學應用
  • 電腦繪圖與電腦輔助設計
  • 電氣與電子工程

指紋

深入研究「BIFEST: A built-in intermediate fault effect sensing and test generation system for cmos bridging faults」主題。共同形成了獨特的指紋。

引用此