BIST-based diagnosis scheme for field programmable gate array interconnect delay faults

Y. L. Peng, C. W. Wu, J. J. Liou, C. T. Huang

研究成果: Article同行評審

4 引文 斯高帕斯(Scopus)

摘要

A new built-in self-test (BIST)-based diagnosis scheme for field programmable gate array (FPGA) interconnect delay faults is proposed. Faulty paths can be located after configuring the output response analyser of the BIST circuit as a scan chain. By analysing these faulty paths, segment fault candidates can be obtained. The proposed diagnosis scheme can find effective test paths to locate faulty segment candidates. Experimental results for an island-style FPGA show high diagnosis resolution in locating the faulty paths, under single- and double-fault models caused by single and double defects, respectively.

原文English
頁(從 - 到)716-723
頁數8
期刊IET Computers and Digital Techniques
1
發行號6
DOIs
出版狀態Published - 2007 十一月 5

All Science Journal Classification (ASJC) codes

  • 軟體
  • 硬體和架構
  • 電氣與電子工程

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