Bit-level systolic arrays for finite-field multiplications

Cheng Wen Wu, Ming Kwang Chang

研究成果: Article同行評審

14 引文 斯高帕斯(Scopus)

摘要

Galois-field multiplication algorithms and their systolic realizations are proposed. Parallel and serial architectures as well as their VLSI implementations are presented. They are based on the standard-basis representation of the Galois-field elements. Our algorithms allow the two operands to enter the systolic arrays in the same order. Only one control signal for the serial systolic array is required as compared to two in the previous design. Our multipliers are more regular and modular, requiring simple control signal, and compact in terms of silicon area; they are well suited to VLSI implementation. Expansion to higher order Galois fields are easier to realize than other multipliers. High throughput rates are achieved due to their systolic array architectures.

原文English
頁(從 - 到)85-92
頁數8
期刊Journal of VLSI Signal Processing
10
發行號1
DOIs
出版狀態Published - 1995 六月 1

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程
  • 訊號處理
  • 資訊系統
  • 理論電腦科學
  • 硬體和架構

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