Block pipeline 2-D IIR filter structures via iteration and retiming

Cheng Wen Wu

研究成果: Conference article同行評審

3 引文 斯高帕斯(Scopus)

摘要

Systolic arrays are presented for real-time 2-D infinite impulse response (IIR) filters, based on the transfer function model. Two-dimensional iteration and retiming techniques are depicted to illustrate block pipelining algorithms, which guarantee high-throughput operation for real-time applications. The systolic realizations are more regular and much faster than the previously published designs. All broadcast data lines can be eliminated, and the arrays can be fully pipelined. The retiming approach is shown to be superior to the iteration method. Examples are given for first- and second-order filters.

原文English
頁(從 - 到)731-734
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
1
出版狀態Published - 1990 十二月 1
事件1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) - New Orleans, LA, USA
持續時間: 1990 五月 11990 五月 3

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程
  • 電子、光磁材料

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