摘要
A turnkey, production circuit simulation ready compact model for cylindrical/surround gate transistors has been developed. The core of the model contains an enhanced surface potential based description of the charge in the channel. Analytical expressions for channel current and terminal charges have been derived. A method to account for quantum confinement in the cylindrical structure in a compact model framework is described. For the first time we present calibration results of such a model to a cylindrical gate technology that also exhibits asymmetric I-V characteristics.
原文 | English |
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頁(從 - 到) | 79-89 |
頁數 | 11 |
期刊 | Solid-State Electronics |
卷 | 67 |
發行號 | 1 |
DOIs | |
出版狀態 | Published - 2012 1月 |
All Science Journal Classification (ASJC) codes
- 電子、光磁材料
- 凝聚態物理學
- 材料化學
- 電氣與電子工程