BSIM4 and BSIM multi-gate progress

Mohan V. Dunga, Chung Hsun Lin, Xuemei Xi, S. Chen, Darsen D. Lu, Ali M. Niknejad, Chenming Hu

研究成果: Paper同行評審

13 引文 斯高帕斯(Scopus)

摘要

New technologies and alternate transistor structures are being developed to extend the CMOS scaling. Device models need to be developed and improved in parallel with the technology advancements to enable an efficient and quick adoption of the new technologies. Some of the recent advances in BSIM4 and BSIM Multi-gate models towards meeting this goal are presented in this paper. Improvements to the BSIM4 model include holistic stress-induced mobility enhancement model and a high-k dynamic behavior model. Preliminary results of the modeling of multi-gate architectures are also presented.

原文English
頁面658-661
頁數4
出版狀態Published - 2006
事件2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings - Boston, MA, United States
持續時間: 2006 五月 72006 五月 11

Other

Other2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings
國家/地區United States
城市Boston, MA
期間06-05-0706-05-11

All Science Journal Classification (ASJC) codes

  • 工程 (全部)

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