Buffer size minimization method considering mix-clock domains and discontinuous data access

Lih-Yih Chiou, Liang Ying Lu, Bo Chi Lin, Alan P. Su

研究成果: Conference contribution

摘要

We propose a method to minimize the buffer size for applications requiring internal multiple clock frequencies and discontinuous data access. The buffer needs not only to handle synchronization between different frequencies, but also to deal with non-first-in-first-out (FIFO) type data access patterns. The proposed method transforms the minimization problem into a graph representation and adopts vertex coloring to minimize the buffer size while meeting the throughput constraints. The experimental results show that the maximum area of the buffer designed by the proposed method is 66.28% smaller than that of a comparable buffer.

原文English
主出版物標題2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
頁面380-383
頁數4
DOIs
出版狀態Published - 2012 十二月 1
事件2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 - Kaohsiung, Taiwan
持續時間: 2012 十二月 22012 十二月 5

出版系列

名字IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

Other2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
國家/地區Taiwan
城市Kaohsiung
期間12-12-0212-12-05

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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