Built-in intermediate voltage testing for CMOS circuits

Jing Jou Tang, Kuen Jong Lee, Bin Da Liu

研究成果: Conference contribution

7 引文 斯高帕斯(Scopus)

摘要

In this paper, we propose 4 new testing technique called built-in intermediate voltage testing for CMOS circuits. This technique provides 4 high quality test which cannot be achieved by conventional functional testing. Three novel circuit designs that can detect faults resulting in intermediate voltage values are presented. These designs can also be used to detect slow transition faults and the metastability of flip-Pops. The detection speed, area overhead, circuit complezity, and the performance impact on the circuits under test are analyzed. The results validate the feasibility of these designs in CMOS testing.

原文English
主出版物標題Proceedings of the 1995 European Conference on Design and Test, EDTC 1995
發行者Association for Computing Machinery, Inc
頁面372-376
頁數5
ISBN(電子)0818670398, 9780818670398
DOIs
出版狀態Published - 1995 三月 6
事件1995 European Conference on Design and Test, EDTC 1995 - Paris, France
持續時間: 1995 三月 61995 三月 9

出版系列

名字Proceedings of the 1995 European Conference on Design and Test, EDTC 1995

Other

Other1995 European Conference on Design and Test, EDTC 1995
國家/地區France
城市Paris
期間95-03-0695-03-09

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程
  • 工業與製造工程

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