Built-in self-repair schemes for flash memories

Yu Ying Hsiao, Chao Hsun Chen, Cheng Wen Wu

研究成果: Article同行評審

15 引文 斯高帕斯(Scopus)

摘要

The advancement of deep submicrometer Integrated circuit manufacturing technology has pushed the use of embedded memory, and the strong demand of embedded nonvolatile memory for system-on-chip and system in package applications has made flash memory increasingly important as well. Nevertheless, the yield loss of memory products caused by deep submicrometer defects and manufacturing uncertainties is still a critical issue. In order to solve the yield issue, built-in self-repair (BISR) has been considered as the most cost-effective solution. However, implementing BISR on flash memories is not trivial. In this paper, we propose BISR schemes for nor flash memory and nand flash memory, respectively. The BISR schemes perform built-in self-test, built-in redundancy analysis, and on-chip repair. For the BISR scheme of nor flash memory, a typical redundancy architecture is assumed, based on which we analyze three existing algorithms and propose a redundancy analysis (RA) algorithm. On the other hand, for nand flash memory, an RA algorithm based on an efficient 2-D redundancy architecture is proposed, and considering the widely used page-mode operation in nand flash memory, a method to discover currently accessed address is also proposed. A simulation tool is also developed, supporting nor flash memory and nand flash memory. The simulation results show that our approach can effectively repair defective memories.

原文English
文章編號5512690
頁(從 - 到)1243-1256
頁數14
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
29
發行號8
DOIs
出版狀態Published - 2010 八月 1

All Science Journal Classification (ASJC) codes

  • 軟體
  • 電腦繪圖與電腦輔助設計
  • 電氣與電子工程

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