Built-In Test and Diagnosis for TSVs with Different Placement Topologies and Crosstalk Impact Ranges

Wen Hsuan Hsu, Michael Andreas Kochte, Kuen Jong Lee

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)

摘要

Through silicon vias (TSVs) play an important role in 3-D chip integration. Effective and efficient testing for correct operation of TSVs is essential for 3-D integrated circuit design. This paper addresses the post-bond test and diagnosis of crosstalk faults among TSVs considering different impact ranges, and proposes a TSV grouping method for rectangular and hexagonal TSV placements such that as many TSVs as possible are tested simultaneously. Based on the results of the TSV grouping, we implement a high-efficiency, low-area-overhead TSV test architecture that reuses the existing boundary scan or IEEE 1500 wrapper cells typically present for prebond testing. Experimental results show the short test and diagnosis time as well as the low area overhead of the proposed test architecture.

原文English
頁(從 - 到)1004-1017
頁數14
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
36
發行號6
DOIs
出版狀態Published - 2017 六月

All Science Journal Classification (ASJC) codes

  • 軟體
  • 電腦繪圖與電腦輔助設計
  • 電氣與電子工程

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