Cache write generate for parallel image processing on shared memory architectures

Craig M. Wittenbrink, Arun K. Somani, Chung Ho Chen

研究成果: Article同行評審

2 引文 斯高帕斯(Scopus)

摘要

We investigate cache write generate, our cache mode invention. We demonstrate that for parallel image processing applications, the new mode improves main memory bandwidth, CPU efficiency, cache hits, and cache latency. We use register level simulations validated by the UW-Proteus system. Many memory, cache, and processor configurations are evaluated.

原文English
頁(從 - 到)1204-1208
頁數5
期刊IEEE Transactions on Image Processing
5
發行號7
DOIs
出版狀態Published - 1996

All Science Journal Classification (ASJC) codes

  • 軟體
  • 電腦繪圖與電腦輔助設計

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