CAM-based VLSI architecture for shared buffer ATM switch with fuzzy controlled buffer management

Chie Dou, Ming-Der Shieh

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

This paper proposes a CAM-based shared buffer ATM switch-on-a-chip architecture that takes network-element internal congestion control into consideration. This internal congestion control includes selective cell discard, priority service scheduling, and fuzzy controlled buffer management. To provide `fair' access to the network resources for all users, the SMXQ buffer control scheme is adopted. The SMXQ scheme assumes a queue length threshold is chosen for the logical queue pertaining to each output port, and if the queue length exceeds the threshold, the arriving cells are discarded. Selective cell discard is performed per port basis when the shared buffer is full or the queue length of a particular output port exceeds its threshold. For each output port, {CLP = 1} cells will be discarded before any {CLP = 0} cells is discarded. The set of chosen queue length thresholds are computed directly by an on-chip fuzzy congestion controller (FCC) in sub microsecond intervals.

原文English
主出版物標題VLSI in Computers and Processors
編輯 Anon
發行者IEEE
頁面149-152
頁數4
出版狀態Published - 1996
事件Proceedings of the 1996 International Conference on Computer Design, ICCD'96 - Austin, TX, USA
持續時間: 1996 十月 71996 十月 9

Other

OtherProceedings of the 1996 International Conference on Computer Design, ICCD'96
城市Austin, TX, USA
期間96-10-0796-10-09

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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