Cascaded complex ADCs with adaptive digital calibration for I/Q mismatch

Yi Tang, Kuang Wei Cheng, Subhanshu Gupta, Jeyanandh Paramesh, David J. Allstot

研究成果: Article同行評審

10 引文 斯高帕斯(Scopus)

摘要

A complex analog-to-digital converter (ADC) intended for digital intermediate frequency (IF) receiver applications digitizes analog signals at IFs with excellent power/bandwidth efficiency. However, it is vulnerable to mismatches between its in-phase and quadrature (I/Q) paths that can dramatically degrade its performance. The proposed solution mitigates I/Q mismatch effects using a complex sigma-delta (ΣΔ) modulator cascaded with 9-bit pipeline converters in each of the I and Q paths. The quantization noise of the first stage complex modulator is eliminated using an adaptive scheme to calibrate finite-impulse response digital filters in the digital noise-cancellation logic block. Although low-pass ΣΔ cascade ADCs are widely used because of their inherent stability and high-order noise shaping, the complex bandpass cascade architecture introduced herein maintains these advantages and doubles the noise shaping bandwidth. Digital calibration also reduces the effects of analog circuit limitations such as finite operational amplifier gain, which enables high performance and low power consumption with high-speed deep-submicrometer CMOS technology. Behavioral simulations of the complex ΣΔ/pipeline cascade bandpass ADC using the adaptive digital calibration algorithm predict a signal-to-noise ratio (SNR) of 78 dB over a 20-MHz signal bandwidth at a sampling rate of 160 MHz in the presence of a 1% I/Q mismatch.

原文English
頁(從 - 到)817-827
頁數11
期刊IEEE Transactions on Circuits and Systems I: Regular Papers
55
發行號3
DOIs
出版狀態Published - 2008 四月 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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