Characteristics and reliability of metal-oxide-semiconductor transistors with various depths of plasma-induced Si recess structure

Jone F. Chen, Yen Lin Tsai, Chun Yen Chen, Hao Tang Hsu, Chia Yu Kao, Hann Ping Hwang

研究成果: Article同行評審

摘要

Device characteristics and hot-carrier-induced device degradation of n-channel MOS transistors with an off-state breakdown voltage of approximately 25V and various Si recess depths introduced by sidewall spacer overetching are investigated. Experimental data show that the depth of the Si recess has small effects on device characteristics. A device with a deeper Si recess has lower substrate current and channel electric field, whereas a greater hot-carrier-induced device degradation and a shorter hot-carrier lifetime are observed. Results of technology computer-aided design simulations suggest that these unexpected observations are related to the severity of plasma damage caused by the sidewall spacer overetching and the difference in topology.

原文English
文章編號04FD01
期刊Japanese journal of applied physics
57
發行號4
DOIs
出版狀態Published - 2018 4月

All Science Journal Classification (ASJC) codes

  • 一般工程
  • 一般物理與天文學

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