Chemical oxide interfacial layer for the high-k-last/gate-last integration scheme

Ying Tsung Chen, Ssu I. Fu, Wen Tai Chiang, Chien Ting Lin, Shih Hung Tsai, Shao Wei Wang, Shoou Jinn Chang

研究成果: Article

8 引文 (Scopus)

摘要

The authors propose a high-k-last with gate-last integration scheme with a chemical oxide interfacial layer (IL). It was found that chemical oxide IL could form Hf-silicate at the high-k/\hbox{IL} interface so as to provide us a larger effective k value and a smaller equivalent oxide thickness (EOT). It was also found that the larger leakage current density for the samples with chemical oxide IL could be effectively suppressed by postdeposition annealing (PDA). Furthermore, it was found that PDA-induced larger EOT could be reduced by optimizing the metal gate stack.

原文English
文章編號6204313
頁(從 - 到)946-948
頁數3
期刊IEEE Electron Device Letters
33
發行號7
DOIs
出版狀態Published - 2012 五月 31

指紋

Oxides
Annealing
Silicates
Leakage currents
Current density
Metals

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

引用此文

Chen, Y. T., Fu, S. I., Chiang, W. T., Lin, C. T., Tsai, S. H., Wang, S. W., & Chang, S. J. (2012). Chemical oxide interfacial layer for the high-k-last/gate-last integration scheme. IEEE Electron Device Letters, 33(7), 946-948. [6204313]. https://doi.org/10.1109/LED.2012.2195292
Chen, Ying Tsung ; Fu, Ssu I. ; Chiang, Wen Tai ; Lin, Chien Ting ; Tsai, Shih Hung ; Wang, Shao Wei ; Chang, Shoou Jinn. / Chemical oxide interfacial layer for the high-k-last/gate-last integration scheme. 於: IEEE Electron Device Letters. 2012 ; 卷 33, 編號 7. 頁 946-948.
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abstract = "The authors propose a high-k-last with gate-last integration scheme with a chemical oxide interfacial layer (IL). It was found that chemical oxide IL could form Hf-silicate at the high-k/\hbox{IL} interface so as to provide us a larger effective k value and a smaller equivalent oxide thickness (EOT). It was also found that the larger leakage current density for the samples with chemical oxide IL could be effectively suppressed by postdeposition annealing (PDA). Furthermore, it was found that PDA-induced larger EOT could be reduced by optimizing the metal gate stack.",
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Chen, YT, Fu, SI, Chiang, WT, Lin, CT, Tsai, SH, Wang, SW & Chang, SJ 2012, 'Chemical oxide interfacial layer for the high-k-last/gate-last integration scheme', IEEE Electron Device Letters, 卷 33, 編號 7, 6204313, 頁 946-948. https://doi.org/10.1109/LED.2012.2195292

Chemical oxide interfacial layer for the high-k-last/gate-last integration scheme. / Chen, Ying Tsung; Fu, Ssu I.; Chiang, Wen Tai; Lin, Chien Ting; Tsai, Shih Hung; Wang, Shao Wei; Chang, Shoou Jinn.

於: IEEE Electron Device Letters, 卷 33, 編號 7, 6204313, 31.05.2012, p. 946-948.

研究成果: Article

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AU - Wang, Shao Wei

AU - Chang, Shoou Jinn

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