Chip implementation of a 1.5-GHz gain-control phase shifter

Hung Chi Wang, Chi Yuan Lu, Jyh Ching Juang, Chun Lin Lu

研究成果: Conference contribution

摘要

This paper presents a 1.5-GHz RF gain-control phase-shifter fabricated in TSMC 0.18-μm CMOS process. The vector-synthesis topology is applied in this work to achieve a wide range phase-shift from 0° -360° for the processed RF signal. A gain-control buffer amplifier is added immediately after the phase-synthesizer to compensate the signal attenuation. The measured maximum attenuation is -21 dB for each of four attenuators which are the core circuits of the phase-synthesizer. The measured gain-control range of the buffer amplifier is around -16 dB at 1.5 GHz. The power consumption of the chip is 14.4mW under 1.8 V power supply. The chip size is 0.74 × 0.68 mm 2.

原文English
主出版物標題3rd International Conference on Innovative Computing Information and Control, ICICIC'08
DOIs
出版狀態Published - 2008 九月 30
事件3rd International Conference on Innovative Computing Information and Control, ICICIC'08 - Dalian, Liaoning, China
持續時間: 2008 六月 182008 六月 20

出版系列

名字3rd International Conference on Innovative Computing Information and Control, ICICIC'08

Other

Other3rd International Conference on Innovative Computing Information and Control, ICICIC'08
國家/地區China
城市Dalian, Liaoning
期間08-06-1808-06-20

All Science Journal Classification (ASJC) codes

  • 電腦科學應用
  • 軟體
  • 控制與系統工程

指紋

深入研究「Chip implementation of a 1.5-GHz gain-control phase shifter」主題。共同形成了獨特的指紋。

引用此