@inproceedings{2d027aee2c1042e9a2a40160322a0613,
title = "Clique partitioning based integrated architecture synthesis for VLSI chips",
abstract = "The tasks as module selection, scheduling and allocation involved in the architecture synthesis problem of VLSI chips are tightly interdependent. Simultaneous optimization of these tasks is necessary for the global solution of a design. In this paper, we present a new graph model for the integrated architecture synthesis problem of VLSI chips and then formulate the problem as a partial clique partition problem and solve it globally using a heuristic. We have tested our approach using examples from the literature and experimental results show that our approach is better then or as good as other published approaches.",
author = "Jou, {Jer Min} and Kuang, {Shiann Rong} and Chen, {Ren Der}",
year = "1993",
month = jan,
day = "1",
doi = "10.1109/VTSA.1993.263627",
language = "English",
series = "International Symposium on VLSI Technology, Systems, and Applications, Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "58--62",
booktitle = "1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers",
address = "United States",
note = "1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 ; Conference date: 12-05-1993 Through 14-05-1993",
}