CMAC neural network chip for color correction

Rong Chang Wen; Jar Shone Ker; Yau Hwang Kuo; Bin Da Liu; Gao Wei Chang

CMAC neural network chip for color correction

Rong Chang Wen, Jar Shone Ker, Yau Hwang Kuo, Bin Da Liu, Gao Wei Chang

研究成果: Paper › 同行評審

摘要

This paper presents the design and implementation of a CMAC neural network chip used in color image reproduction systems for color correction. An effective address mapping procedure is proposed to implement the hardware architecture of CMAC model, which has the advantages of high processing speed and low chip area overhead. VHDL-based high-level synthesis approach is employed for the synthesis of logic circuit of CMAC chip.

原文	English
頁面	1943-1946
頁數	4
出版狀態	Published - 1994
事件	Proceedings of the 1994 IEEE International Conference on Neural Networks. Part 1 (of 7) - Orlando, FL, USA 持續時間: 1994 6月 27 → 1994 6月 29

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Other	Proceedings of the 1994 IEEE International Conference on Neural Networks. Part 1 (of 7)
城市	Orlando, FL, USA
期間	94-06-27 → 94-06-29

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title = "CMAC neural network chip for color correction",

abstract = "This paper presents the design and implementation of a CMAC neural network chip used in color image reproduction systems for color correction. An effective address mapping procedure is proposed to implement the hardware architecture of CMAC model, which has the advantages of high processing speed and low chip area overhead. VHDL-based high-level synthesis approach is employed for the synthesis of logic circuit of CMAC chip.",

author = "Wen, {Rong Chang} and Ker, {Jar Shone} and Kuo, {Yau Hwang} and Liu, {Bin Da} and Chang, {Gao Wei}",

year = "1994",

language = "English",

pages = "1943--1946",

note = "Proceedings of the 1994 IEEE International Conference on Neural Networks. Part 1 (of 7) ; Conference date: 27-06-1994 Through 29-06-1994",

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TY - CONF

T1 - CMAC neural network chip for color correction

AU - Wen, Rong Chang

AU - Ker, Jar Shone

AU - Kuo, Yau Hwang

AU - Liu, Bin Da

AU - Chang, Gao Wei

PY - 1994

Y1 - 1994

N2 - This paper presents the design and implementation of a CMAC neural network chip used in color image reproduction systems for color correction. An effective address mapping procedure is proposed to implement the hardware architecture of CMAC model, which has the advantages of high processing speed and low chip area overhead. VHDL-based high-level synthesis approach is employed for the synthesis of logic circuit of CMAC chip.

AB - This paper presents the design and implementation of a CMAC neural network chip used in color image reproduction systems for color correction. An effective address mapping procedure is proposed to implement the hardware architecture of CMAC model, which has the advantages of high processing speed and low chip area overhead. VHDL-based high-level synthesis approach is employed for the synthesis of logic circuit of CMAC chip.

UR - http://www.scopus.com/inward/record.url?scp=0028744430&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028744430&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0028744430

SP - 1943

EP - 1946

T2 - Proceedings of the 1994 IEEE International Conference on Neural Networks. Part 1 (of 7)

Y2 - 27 June 1994 through 29 June 1994

ER -

CMAC neural network chip for color correction

摘要

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All Science Journal Classification (ASJC) codes

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