CMOS 40GHz divide-by-5 injection-locked frequency divider

P. K. Tsai, Tzuen-Hsi Huang, Y. H. Pang

研究成果: Article

10 引文 斯高帕斯(Scopus)

摘要

A 40GHz divide-by-5 injection-locked frequency divider fabricated in a CMOS 0.18m process is presented. By utilising a series-LC bandpass filter that is connected to the common-mode node of the differential injection pair to bypass the unwanted second harmonic and produce high impedance for the desired fourth-order harmonic, the fourth-order harmonic (4f0) is peaked and mixed with input signals (at 5f0) to achieve the output frequency f0 (=5f0-4f0). With an injection power of -3dBm, the measured maximum locking range is 735MHz at a tuning voltage of 0.8V. The total locking range covers 39.36-42.1GHz as the tuning voltage rises from 0 to 1.8V. This divider consumes 18mW at 1V supply voltage.

原文English
頁(從 - 到)1003-1004
頁數2
期刊Electronics Letters
46
發行號14
DOIs
出版狀態Published - 2010 七月 8

    指紋

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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