Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs

Jai-Ming Lin, Chien Yu Huang, Jhih Ying Yang

研究成果: Conference contribution

1 引文 (Scopus)

摘要

This paper addresses a 3D floorplanning methodology, which considers floorplanning and powerplanning at the same time for Multiple Supply Voltage (MSV) circuits. Physical design becomes more complex for MSV designs since modules with the same power domain have to be placed at close locations in 3D space to facilitate powerplanning and reduce IR-drop, which would deteriorate wirelength. By properly partitioning modules of the same power domain into several voltage islands and increasing overlap area of the voltage islands in contiguous dies, we can reduce routing resource usage without increasing wirelength significantly. Further, unlike previous works, our approach not only can handle a netlist with soft modules and hard modules but also can meet the fixed-outline constraint. The experimental results show that our methodology gets better results than other approach in designs with single voltage domain and is also promising for MSV designs.

原文English
主出版物標題Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
發行者Institute of Electrical and Electronics Engineers Inc.
頁面1339-1344
頁數6
2018-January
ISBN(電子)9783981926316
DOIs
出版狀態Published - 2018 四月 19
事件2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 - Dresden, Germany
持續時間: 2018 三月 192018 三月 23

Other

Other2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
國家Germany
城市Dresden
期間18-03-1918-03-23

指紋

Electric potential
Module
Networks (circuits)
Methodology
Resources
Routing
Partitioning

All Science Journal Classification (ASJC) codes

  • Safety, Risk, Reliability and Quality
  • Hardware and Architecture
  • Software
  • Information Systems and Management

引用此文

Lin, J-M., Huang, C. Y., & Yang, J. Y. (2018). Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs. 於 Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 (卷 2018-January, 頁 1339-1344). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/DATE.2018.8342221
Lin, Jai-Ming ; Huang, Chien Yu ; Yang, Jhih Ying. / Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs. Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. 卷 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. 頁 1339-1344
@inproceedings{a3b2ff19346446eab84f5fae3726f09e,
title = "Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs",
abstract = "This paper addresses a 3D floorplanning methodology, which considers floorplanning and powerplanning at the same time for Multiple Supply Voltage (MSV) circuits. Physical design becomes more complex for MSV designs since modules with the same power domain have to be placed at close locations in 3D space to facilitate powerplanning and reduce IR-drop, which would deteriorate wirelength. By properly partitioning modules of the same power domain into several voltage islands and increasing overlap area of the voltage islands in contiguous dies, we can reduce routing resource usage without increasing wirelength significantly. Further, unlike previous works, our approach not only can handle a netlist with soft modules and hard modules but also can meet the fixed-outline constraint. The experimental results show that our methodology gets better results than other approach in designs with single voltage domain and is also promising for MSV designs.",
author = "Jai-Ming Lin and Huang, {Chien Yu} and Yang, {Jhih Ying}",
year = "2018",
month = "4",
day = "19",
doi = "10.23919/DATE.2018.8342221",
language = "English",
volume = "2018-January",
pages = "1339--1344",
booktitle = "Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
address = "United States",

}

Lin, J-M, Huang, CY & Yang, JY 2018, Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs. 於 Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. 卷 2018-January, Institute of Electrical and Electronics Engineers Inc., 頁 1339-1344, 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018, Dresden, Germany, 18-03-19. https://doi.org/10.23919/DATE.2018.8342221

Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs. / Lin, Jai-Ming; Huang, Chien Yu; Yang, Jhih Ying.

Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. 卷 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. p. 1339-1344.

研究成果: Conference contribution

TY - GEN

T1 - Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs

AU - Lin, Jai-Ming

AU - Huang, Chien Yu

AU - Yang, Jhih Ying

PY - 2018/4/19

Y1 - 2018/4/19

N2 - This paper addresses a 3D floorplanning methodology, which considers floorplanning and powerplanning at the same time for Multiple Supply Voltage (MSV) circuits. Physical design becomes more complex for MSV designs since modules with the same power domain have to be placed at close locations in 3D space to facilitate powerplanning and reduce IR-drop, which would deteriorate wirelength. By properly partitioning modules of the same power domain into several voltage islands and increasing overlap area of the voltage islands in contiguous dies, we can reduce routing resource usage without increasing wirelength significantly. Further, unlike previous works, our approach not only can handle a netlist with soft modules and hard modules but also can meet the fixed-outline constraint. The experimental results show that our methodology gets better results than other approach in designs with single voltage domain and is also promising for MSV designs.

AB - This paper addresses a 3D floorplanning methodology, which considers floorplanning and powerplanning at the same time for Multiple Supply Voltage (MSV) circuits. Physical design becomes more complex for MSV designs since modules with the same power domain have to be placed at close locations in 3D space to facilitate powerplanning and reduce IR-drop, which would deteriorate wirelength. By properly partitioning modules of the same power domain into several voltage islands and increasing overlap area of the voltage islands in contiguous dies, we can reduce routing resource usage without increasing wirelength significantly. Further, unlike previous works, our approach not only can handle a netlist with soft modules and hard modules but also can meet the fixed-outline constraint. The experimental results show that our methodology gets better results than other approach in designs with single voltage domain and is also promising for MSV designs.

UR - http://www.scopus.com/inward/record.url?scp=85048764562&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85048764562&partnerID=8YFLogxK

U2 - 10.23919/DATE.2018.8342221

DO - 10.23919/DATE.2018.8342221

M3 - Conference contribution

AN - SCOPUS:85048764562

VL - 2018-January

SP - 1339

EP - 1344

BT - Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Lin J-M, Huang CY, Yang JY. Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs. 於 Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. 卷 2018-January. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1339-1344 https://doi.org/10.23919/DATE.2018.8342221