TY - JOUR
T1 - Combined 2-D transform and quantization architectures for H.264 video coders
AU - Lin, Heng Yao
AU - Chao, Yi Chih
AU - Chen, Che Hong
AU - Liu, Bin Da
AU - Yang, Jar Ferr
PY - 2005
Y1 - 2005
N2 - In this paper, the low-complexity hardware architectures of 4×4 forward and inverse transforms with integrated quantizer and dequantizer for H.264 advanced video coders (AVC) are proposed. By applying the regularity of the quantization matrix, the quantization can be merged into transform step, which results in the reduction of the hardware complexity in VLSI implementation. The proposed integrated transforms have been synthesized with TSMC 0.35 μm technology. Simulation results show that it can achieve 256 M samples/sec at 32 MHz in encoder part and 448 M samples/sec at 56 MHz in decoder part, respectively.
AB - In this paper, the low-complexity hardware architectures of 4×4 forward and inverse transforms with integrated quantizer and dequantizer for H.264 advanced video coders (AVC) are proposed. By applying the regularity of the quantization matrix, the quantization can be merged into transform step, which results in the reduction of the hardware complexity in VLSI implementation. The proposed integrated transforms have been synthesized with TSMC 0.35 μm technology. Simulation results show that it can achieve 256 M samples/sec at 32 MHz in encoder part and 448 M samples/sec at 56 MHz in decoder part, respectively.
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U2 - 10.1109/ISCAS.2005.1464959
DO - 10.1109/ISCAS.2005.1464959
M3 - Conference article
AN - SCOPUS:33646420685
SN - 0271-4310
SP - 1802
EP - 1805
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
M1 - 1464959
T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
Y2 - 23 May 2005 through 26 May 2005
ER -