TY - JOUR
T1 - Combined decoding and flexible transform designs for effective H.264/AVC decoders
AU - Chao, Yi Chih
AU - Wei, Shih Tse
AU - Yang, Jar Ferr
AU - Liu, Bin Da
PY - 2007
Y1 - 2007
N2 - In this paper, we propose combined decoding architecture and high-throughput flexible transform design to effectively decode the residual data for H.264/AVC decoders. The inverse quantization (IQ) procedure is combined with context-based adaptive variable length coding (CAVLC) decoder to efficiently achieve the simplification. Besides, the flexible transform architecture is also proposed for effective computation of all transforms needed in H.264/AVC decoders. Since all the transforms are realized in the same architecture, the flexible transform design with the throughput of 8 pixels/sec needs fewer logic gate counts. Simulation results show that the implemented gate count is 18.6k and the maximum operating frequency is 125 MHz. For real-time requirements, this proposed design achieves 4VGA (1280×960)@30 frames/sec in the worst case.
AB - In this paper, we propose combined decoding architecture and high-throughput flexible transform design to effectively decode the residual data for H.264/AVC decoders. The inverse quantization (IQ) procedure is combined with context-based adaptive variable length coding (CAVLC) decoder to efficiently achieve the simplification. Besides, the flexible transform architecture is also proposed for effective computation of all transforms needed in H.264/AVC decoders. Since all the transforms are realized in the same architecture, the flexible transform design with the throughput of 8 pixels/sec needs fewer logic gate counts. Simulation results show that the implemented gate count is 18.6k and the maximum operating frequency is 125 MHz. For real-time requirements, this proposed design achieves 4VGA (1280×960)@30 frames/sec in the worst case.
UR - http://www.scopus.com/inward/record.url?scp=34548854801&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=34548854801&partnerID=8YFLogxK
U2 - 10.1109/iscas.2007.378095
DO - 10.1109/iscas.2007.378095
M3 - Conference article
AN - SCOPUS:34548854801
SN - 0271-4310
SP - 3135
EP - 3138
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
M1 - 4253343
T2 - 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007
Y2 - 27 May 2007 through 30 May 2007
ER -