Computationally efficient compact model for ferroelectric field-effect transistors to simulate the online training of neural networks

Darsen Duane Lu, Sourav De, Mohammed Aftab Baig, Bo Han Qiu, Yao Jen Lee

研究成果: Article同行評審

15 引文 斯高帕斯(Scopus)

摘要

In this paper, a compact drain current formulation that is simple and adequately computationally efficient for the simulation of neural network online training was developed for the ferroelectric memory transistor. Tri-gate ferroelectric field-effect transistors (FETs) with Hf0.5Zr0.5O2 gate insulators were fabricated with a gate-first high-k metal gate CMOS process. Ferroelectric switching was confirmed with double sweep and pulse programming and erasure measurements. Novel characterization scheme for drain current was proposed with minimal alteration of ferroelectric state in subthreshold for accurate threshold voltage measurements. The resultant threshold voltage exhibited highly linear and symmetric across multilevel states. The proposed compact formulation accurately captured the FET gate-bias dependence by considering the effects of series resistance, Coulomb scattering, and vertical field dependent mobility degradation.

原文English
文章編號095007
期刊Semiconductor Science and Technology
35
發行號9
DOIs
出版狀態Published - 2020 9月

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 凝聚態物理學
  • 電氣與電子工程
  • 材料化學

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