Concurrent timing optimization of latch-based digital systems

Hong Yean Hsieh, Wentai Liu, Ralph K. Cavin, C. Thomas Gray

研究成果: Paper同行評審

7 引文 斯高帕斯(Scopus)

摘要

Many techniques have been proposed to optimize digital system timing. Each technique can be advantageous in particular applications, however they are most often applied individually rather than concurrently. The framework presented here allows for concurrent timing optimization using retiming, intentional clock skew, and wave pipelining for latch-based designed systems with single or multi-phase clocking. This optimization is formulated as a mixed integer linear program. Our integrated framework also includes a new optimization technique called resynchronization which allows for the insertion of latches in the shortest paths and thus avoids race conditions. Our work has been applied to several designs and is able to significantly reduce the clock period.

原文English
頁面680-685
頁數6
出版狀態Published - 1995
事件Proceedings of the 1995 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Austin, TX, USA
持續時間: 1995 10月 21995 10月 4

Conference

ConferenceProceedings of the 1995 IEEE International Conference on Computer Design: VLSI in Computers & Processors
城市Austin, TX, USA
期間95-10-0295-10-04

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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