Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement

Bing Yang Lin, Wan Ting Chiang, Cheng Wen Wu, Mincent Lee, Hung Chih Lin, Ching Nen Peng, Min Jer Wang

研究成果: Article同行評審

2 引文 斯高帕斯(Scopus)

摘要

Three-dimensional stacked memory stacking logic and memory dies are one of the most promising 3-D integration applications. This paper proposes two memory redundancy schemes to improve the yield of channelbased 3-D stacked DRAM by sharing spare memory across dies and satisfying channel constraints at the same time. The proposed schemes achieve much higher yield with very small area overhead than other memory redundancy schemes.

原文English
文章編號7154435
頁(從 - 到)30-39
頁數10
期刊IEEE Design and Test
33
發行號2
DOIs
出版狀態Published - 2016 四月 1

All Science Journal Classification (ASJC) codes

  • 軟體
  • 硬體和架構
  • 電氣與電子工程

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