Constraints for using IDDQ testing to detect CMOS bridging faults

Kuen-Jong Lee, M. A. Breuer

研究成果: Paper

11 引文 (Scopus)

摘要

Detecting CMOS bridging faults (BFs) using IDDQ testing, or the current supply monitoring method (CSM), has recently received much attention. One fundamental question that needs to be answered for this technique is 'what circuits does it apply to'. Previously the authors presented a set of constraints on circuits and their test environment that formed a sufficient condition for using CSM to detect all single and multiple irredundant BFs. In this paper they show that if any of these constraints are removed then circuits exist for which CSM cannot give correct results. Two special classes of circuits, domino logic and synchronous sequential circuits, are discussed in detail.

原文English
頁面303-308
頁數6
DOIs
出版狀態Published - 1991 一月 1
事件1991 IEEE VLSI Test Symposium: Chip-to-System Test Concerns for the 90''s, VTEST 1991 - Atlantic City, United States
持續時間: 1991 四月 151991 四月 17

Conference

Conference1991 IEEE VLSI Test Symposium: Chip-to-System Test Concerns for the 90''s, VTEST 1991
國家United States
城市Atlantic City
期間91-04-1591-04-17

指紋

Networks (circuits)
Monitoring
Testing
Sequential circuits
Logic circuits

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

引用此文

Lee, K-J., & Breuer, M. A. (1991). Constraints for using IDDQ testing to detect CMOS bridging faults. 303-308. 論文發表於 1991 IEEE VLSI Test Symposium: Chip-to-System Test Concerns for the 90''s, VTEST 1991, Atlantic City, United States. https://doi.org/10.1109/VTEST.1991.208175
Lee, Kuen-Jong ; Breuer, M. A. / Constraints for using IDDQ testing to detect CMOS bridging faults. 論文發表於 1991 IEEE VLSI Test Symposium: Chip-to-System Test Concerns for the 90''s, VTEST 1991, Atlantic City, United States.6 p.
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Lee, K-J & Breuer, MA 1991, 'Constraints for using IDDQ testing to detect CMOS bridging faults', 論文發表於 1991 IEEE VLSI Test Symposium: Chip-to-System Test Concerns for the 90''s, VTEST 1991, Atlantic City, United States, 91-04-15 - 91-04-17 頁 303-308. https://doi.org/10.1109/VTEST.1991.208175

Constraints for using IDDQ testing to detect CMOS bridging faults. / Lee, Kuen-Jong; Breuer, M. A.

1991. 303-308 論文發表於 1991 IEEE VLSI Test Symposium: Chip-to-System Test Concerns for the 90''s, VTEST 1991, Atlantic City, United States.

研究成果: Paper

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Lee K-J, Breuer MA. Constraints for using IDDQ testing to detect CMOS bridging faults. 1991. 論文發表於 1991 IEEE VLSI Test Symposium: Chip-to-System Test Concerns for the 90''s, VTEST 1991, Atlantic City, United States. https://doi.org/10.1109/VTEST.1991.208175