Controller architecture for low-power, low-latency DRAM with built-in cache

Zhi Yong Liu, Hsiu Chuan Shih, Bing Yang Lin, Cheng Wen Wu

研究成果: Article

1 引文 斯高帕斯(Scopus)

摘要

Memory wall is a critical issue for many today's electronic systems. Tiered latency DRAM with asymmetric bit lines was proposed to optimize the power and latency. This paper proposes a controller architecture for the tiered latency DRAM in which the small array is operated like a cache. - Jin-Fu Li, National Central University

原文English
文章編號7397924
頁(從 - 到)69-78
頁數10
期刊IEEE Design and Test
34
發行號2
DOIs
出版狀態Published - 2017 四月 1

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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