Copper plating process for through silicon via with high aspect ratio in advanced packaging

Yu Hung Huang, Huei-Huang Lee, Sheng-Jye Hwang, Durn Yuan Huang

研究成果: Conference contribution

摘要

Through silicon via (TSV) is a technology which allows devices to be connected three-dimensionally. Three dimensional vertical integration using TSV Cu interconnect can greatly increase the packaging density and is one of the most advanced and promising technologies for future IC packaging. However, Cu filling of void free through silicon via with high aspect ratio (AR≥10) has been a challenge for a long time. In this paper, successful fabrication of void free TSV with very high aspect ratio was demonstrated via electroplating process. Proper equipment and processing conditions for electroplating are required. The same equipment and similar chemicals and process conditions could also be applied to fabricate high quality redistribution line technology (RDL).

原文English
主出版物標題Proceedings of the ASME InterPack Conference 2009, IPACK2009
頁面9-14
頁數6
DOIs
出版狀態Published - 2010 六月 25
事件2009 ASME InterPack Conference, IPACK2009 - San Francisco, CA, United States
持續時間: 2009 七月 192009 七月 23

出版系列

名字Proceedings of the ASME InterPack Conference 2009, IPACK2009
1

Other

Other2009 ASME InterPack Conference, IPACK2009
國家/地區United States
城市San Francisco, CA
期間09-07-1909-07-23

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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