Copper plating process for through silicon via with high aspect ratio in advanced packaging

Yu Hung Huang; Huei-Huang Lee; Sheng-Jye Hwang; Durn Yuan Huang

doi:10.1115/InterPACK2009-89163

Copper plating process for through silicon via with high aspect ratio in advanced packaging

Yu Hung Huang, Huei-Huang Lee, Sheng-Jye Hwang, Durn Yuan Huang

研究成果: Conference contribution

摘要

Through silicon via (TSV) is a technology which allows devices to be connected three-dimensionally. Three dimensional vertical integration using TSV Cu interconnect can greatly increase the packaging density and is one of the most advanced and promising technologies for future IC packaging. However, Cu filling of void free through silicon via with high aspect ratio (AR≥10) has been a challenge for a long time. In this paper, successful fabrication of void free TSV with very high aspect ratio was demonstrated via electroplating process. Proper equipment and processing conditions for electroplating are required. The same equipment and similar chemicals and process conditions could also be applied to fabricate high quality redistribution line technology (RDL).

原文	English
主出版物標題	Proceedings of the ASME InterPack Conference 2009, IPACK2009
頁面	9-14
頁數	6
DOIs	https://doi.org/10.1115/InterPACK2009-89163
出版狀態	Published - 2010 6月 25
事件	2009 ASME InterPack Conference, IPACK2009 - San Francisco, CA, United States 持續時間: 2009 7月 19 → 2009 7月 23

出版系列

名字	Proceedings of the ASME InterPack Conference 2009, IPACK2009
卷	1

Other

Other	2009 ASME InterPack Conference, IPACK2009
國家/地區	United States
城市	San Francisco, CA
期間	09-07-19 → 09-07-23

All Science Journal Classification (ASJC) codes

硬體和架構
電氣與電子工程

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10.1115/InterPACK2009-89163

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引用此

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title = "Copper plating process for through silicon via with high aspect ratio in advanced packaging",

abstract = "Through silicon via (TSV) is a technology which allows devices to be connected three-dimensionally. Three dimensional vertical integration using TSV Cu interconnect can greatly increase the packaging density and is one of the most advanced and promising technologies for future IC packaging. However, Cu filling of void free through silicon via with high aspect ratio (AR≥10) has been a challenge for a long time. In this paper, successful fabrication of void free TSV with very high aspect ratio was demonstrated via electroplating process. Proper equipment and processing conditions for electroplating are required. The same equipment and similar chemicals and process conditions could also be applied to fabricate high quality redistribution line technology (RDL).",

author = "Huang, {Yu Hung} and Huei-Huang Lee and Sheng-Jye Hwang and Huang, {Durn Yuan}",

year = "2010",

month = jun,

day = "25",

doi = "10.1115/InterPACK2009-89163",

language = "English",

isbn = "9780791843598",

series = "Proceedings of the ASME InterPack Conference 2009, IPACK2009",

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note = "2009 ASME InterPack Conference, IPACK2009 ; Conference date: 19-07-2009 Through 23-07-2009",

}

Huang, YH, Lee, H-H, Hwang, S-J & Huang, DY 2010, Copper plating process for through silicon via with high aspect ratio in advanced packaging. 於 Proceedings of the ASME InterPack Conference 2009, IPACK2009. Proceedings of the ASME InterPack Conference 2009, IPACK2009, 卷 1, 頁 9-14, 2009 ASME InterPack Conference, IPACK2009, San Francisco, CA, United States, 09-07-19. https://doi.org/10.1115/InterPACK2009-89163

TY - GEN

T1 - Copper plating process for through silicon via with high aspect ratio in advanced packaging

AU - Huang, Yu Hung

AU - Lee, Huei-Huang

AU - Hwang, Sheng-Jye

AU - Huang, Durn Yuan

PY - 2010/6/25

Y1 - 2010/6/25

N2 - Through silicon via (TSV) is a technology which allows devices to be connected three-dimensionally. Three dimensional vertical integration using TSV Cu interconnect can greatly increase the packaging density and is one of the most advanced and promising technologies for future IC packaging. However, Cu filling of void free through silicon via with high aspect ratio (AR≥10) has been a challenge for a long time. In this paper, successful fabrication of void free TSV with very high aspect ratio was demonstrated via electroplating process. Proper equipment and processing conditions for electroplating are required. The same equipment and similar chemicals and process conditions could also be applied to fabricate high quality redistribution line technology (RDL).

AB - Through silicon via (TSV) is a technology which allows devices to be connected three-dimensionally. Three dimensional vertical integration using TSV Cu interconnect can greatly increase the packaging density and is one of the most advanced and promising technologies for future IC packaging. However, Cu filling of void free through silicon via with high aspect ratio (AR≥10) has been a challenge for a long time. In this paper, successful fabrication of void free TSV with very high aspect ratio was demonstrated via electroplating process. Proper equipment and processing conditions for electroplating are required. The same equipment and similar chemicals and process conditions could also be applied to fabricate high quality redistribution line technology (RDL).

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DO - 10.1115/InterPACK2009-89163

M3 - Conference contribution

AN - SCOPUS:77953741540

SN - 9780791843598

T3 - Proceedings of the ASME InterPack Conference 2009, IPACK2009

SP - 9

EP - 14

BT - Proceedings of the ASME InterPack Conference 2009, IPACK2009

T2 - 2009 ASME InterPack Conference, IPACK2009

Y2 - 19 July 2009 through 23 July 2009

ER -

Copper plating process for through silicon via with high aspect ratio in advanced packaging

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