Cost-effective global fault-tolerant multiprocessors+

Chu Sing Yang, Shun Yue Wu

研究成果: Paper

摘要

The global design approach we propose for fault-tolerant multiprocessors is cost-effective, while assuring full spare utilization during a proper reconfiguration process. Use of task reassignment during reconfiguration helps keep system costs effective and system size expandable easily. Our scheme is topology-independent; that is, any multiprocessor system can be applied. As compared with previous work, the proposed scheme can achieve higher or the same reliability at less extra hardware cost.

原文English
頁面205-213
頁數9
出版狀態Published - 1994 十二月 1
事件Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN) - Kanazawa, Jpn
持續時間: 1994 十二月 141994 十二月 16

Other

OtherProceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN)
城市Kanazawa, Jpn
期間94-12-1494-12-16

指紋

Costs
Topology
Hardware

All Science Journal Classification (ASJC) codes

  • Computer Science(all)

引用此文

Yang, C. S., & Wu, S. Y. (1994). Cost-effective global fault-tolerant multiprocessors+. 205-213. 論文發表於 Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN), Kanazawa, Jpn, .
Yang, Chu Sing ; Wu, Shun Yue. / Cost-effective global fault-tolerant multiprocessors+. 論文發表於 Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN), Kanazawa, Jpn, .9 p.
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Yang, CS & Wu, SY 1994, 'Cost-effective global fault-tolerant multiprocessors+', 論文發表於 Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN), Kanazawa, Jpn, 94-12-14 - 94-12-16 頁 205-213.

Cost-effective global fault-tolerant multiprocessors+. / Yang, Chu Sing; Wu, Shun Yue.

1994. 205-213 論文發表於 Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN), Kanazawa, Jpn, .

研究成果: Paper

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Yang CS, Wu SY. Cost-effective global fault-tolerant multiprocessors+. 1994. 論文發表於 Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN), Kanazawa, Jpn, .